The present invention relates to a method for fabricating a semiconductor memory device; and more particularly, to a method for fabricating a metal line of a semiconductor memory device.
As semiconductor memory devices have become highly integrated, semiconductor memory devices need to operate at higher speeds. Recently, a method for reducing resistance of a metal line has been developed to fabricate a flash memory device which can operate at high speed. As a part of the method, a metal having low surface resistance (Rs) such as tungsten, aluminum, or copper is used.
FIGS. 1A and 1B are cross-sectional views illustrating a typical method for fabricating a semiconductor memory device (e.g., NAND flash memory). As shown in FIG. 1A, a plurality of gate structures 17 functioning as gates of the memory device are formed over a substrate 10. Each of the gate structures 17 is formed by sequentially stacking a tunnel oxide layer 11, a floating gate 12, a dielectric layer 13, a control gate 14, and a hard mask 15.
Although FIG. 1A illustrates only the gates of the memory cell, the semiconductor memory device includes a plurality of memory cells formed with a string structure. A drain selection transistor (not shown) connected to a bit line and a source selection transistor (not shown) connected to a common source line are formed over sidewalls of the string structure.
An insulation layer 18 is formed over a height difference of an upper surface of the above resulting structure including the gate structures 17. The insulation layer 18 serves a role as an etch barrier layer during a subsequent etching process. A first insulation layer 19 is formed over the insulation layer 18 to cover the above resulting structure including the gate structures 17.
A portion of the first insulation layer 19 and the insulation layer 18 is etched to form a first contact hole (not shown) exposing an active region, i.e., a source region of the source selection transistor, of the substrate 10. A source contact plug 20 isolated in the first contact hole is formed.
A second insulation layer 21 is formed over the first insulation layer 19 that is already patterned. A portion of the first insulation layer 19, the second insulation layer 21, and the insulation layer 18 is etched to form a second contact hole (not shown) exposing the active region, i.e., a drain region of the drain selection transistor, of the substrate 10. A drain contact plug 22 isolated in the second contact hole is formed.
An etch stop layer 23 and a third insulation layer 24 are formed over the second insulation layer 21 that is already patterned. A dual damascene process is performed to etch the third insulation layer 24, the etch stop layer 23, and the second insulation layer 21 that is already patterned. As a result, trenches and via contact holes are formed. Hereinafter, the trenches and the via contact holes will be together referred to as openings 25.
As shown in FIG. 1B, a plurality of diffusion barrier layers 26 (see FIG. 2) are formed over inner surfaces of the openings 25. A metal interconnection material having low surface resistance such as tungsten is formed over an entire surface of the above resulting structure including the third insulation layer 24 that is already patterned to fill the openings 25.
The metal interconnection material is planarized to form a plurality of metal lines 27 respectively connected to the source contact plug 20 and the drain contact plug 22. A fourth insulation layer 28 is formed over the third insulation layer 24 that is already patterned including the metal lines 27. The fourth insulation layer 28 serves a role as a passivation layer protecting the metal lines 27.
Since a physical vapor deposition (PVD) process is performed to form the fourth insulation layer 28 using a high density plasma (HDP) layer after the metal lines 27 are formed, surfaces of the metal lines 27 may be damaged by a hydrogen (H2) gas or plasma. Thus, resistance may be increased.
The typical method for fabricating the semiconductor memory device shown in FIGS. 1A and 1B have the following limitations. These limitations will be explained in relation to FIG. 2. FIG. 2 is a cross-sectional view enlarging a portion ‘A’ shown in FIG. 1B.
According to the typical method, a dual damascene process is performed to form the metal lines. The dual damascene process generates two elements which block a fast transmission of electric charges of the metal lines. One is high surface resistance of a titanium (Ti)/titanium nitride L (TiN) layer forming the diffusion barrier layers 26. The other one is an increase in capacitance by a nitride layer forming the etch stop layer 23. Accordingly, it is difficult to attain a high speed operation of the typical semiconductor memory device, which is required for large-scale integration.